1. Field of the Invention
The present invention relates to a fast cycle RAM or FCRAM (Fast Cycle Random Access Memory, application for registration trademark pending by Fujitsu Co. Ltd.) whereby the random address cycle can be shortened, and in particular, to an FCRAM which is capable of switching between column access mode and random access mode.
2. Description of the Related Art
In a conventional DRAM, data is read out from a memory cell to sense amplifiers by operating a row circuit in response to a row address and activating a word line and sense amplifiers, whereupon a column circuit is operated in response to a column address, and data is output from the selected sense amplifiers. When data output has been completed, reset operations or precharge operations are conducted in the row circuit and the column circuit. Therefore, generally, it is necessary to maintain the word line and the sense amplifiers in an activated state until the required data output has been completed, and hence it has not been possible to shorten the cycle time of the random access operation (random address cycle time) involved in changing the row address.
FIG. 20 is a timing chart illustrating a page mode read operation in a conventional DRAM. In page mode in a conventional DRAM, a row address is supplied in synchronism with a row address strobe signal RAS, a row decode operation is activated, a single work line is activated, and a plurality of data bits are output by means of a toggle operation of a column address strobe signal CAS, whilst sense amplifiers latch the corresponding data. A column addresses are generated internally each time the column address strobe signal CAS performs a toggle operation, and hence plural data are output in a continuous fashion. Consequently, the virtual sequence access time tRAC is shortened by means of the data in memory cells connected to the same word line being output continuously from a row of sense amplifiers in an activated state.
FIG. 21 is a timing chart illustrating a read operation in a conventional synchronous DRAM (SDRAM) in burst mode. FIG. 21 shows a case where the burst length is 2. In this read operation, a row decoder is activated and a single word line is activated, in response to an active command ACTV issued in synchronism with the rising edge of a clock CLOCK. Thereupon, whilst the sense amplifiers are activated and latch the corresponding data, a column decoder is activated in response to a read command READ and data is latched in a CAS circuit and then output. Since the burst length is 2, two data bits are output consecutively for each READ command. Thereupon, in response to the subsequent read command READ, the operations of activating the column decoder with respect to the relevant column address, and then latching and outputting the data, are carried out in a continuous fashion.
In the case of a synchronous DRAM, the column decode and data latch operations for consecutive read commands can be overlapped each other by using a pipeline structure inside the circuit for column system, and the data output is speeded up accordingly.
In the case of either of the two readout operations described above, a plurality of data bits on the same word line can be read out at high speed by first activating a word line and activating sense amplifiers in accordance with a row address, and holding the corresponding data, whilst repeating the CAS system operation. In a write operation, essentially, a single word line is activated, and a plurality of write data bits are written to the memory cells of this word line via sense amplifiers.
Therefore, when used in a cache memory, or the like, in a generic system, increases in speed can be achieved even in the conventional readout and write operations described above. However, in cases where the volume of data is very large and the address may shift in any direction, such as the main memory of a supercomputer or three-dimensional graphics applications, it is necessary for the memory device to conduct random access operations at frequent intervals. These random access operations require a long time from activation of a word line until reset of the word line after data readout, and hence they represent an obstacle to achieving high speeds.
Therefore, the present applicants have proposed a fast cycle RAM (FCRAM) which is capable of shortening the cycle time associated with the random access operation. This has been reported, for example, in Nikkei Electronics, Jun. 15, 1998, pp. 163-171, or 1998 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, pp. 22-25. The present applicants have also taken out International Patent Application JP98/02443, dated Jun. 3, 1998.
In this memory device, the random address cycle time has been compressed significantly by changing the memory/core architecture. The basic operation of this device involves continuous implementation of an operational sequence involving the steps of, in response to a single READ or WRITE command, or the like, activating a word line, activating sense amplifiers, latching and outputting data, and performing a reset operation so as to output data for burst length or to write data for burst length. Therefore, the activated state of the word line and sense amplifiers is not maintained unlike the prior art.
In a FCRAM, in order to shorten the random address cycle time, a plurality of data bits corresponding to the burst length is transferred simultaneously from the sense amplifiers to the CAS circuit section with respect to a single output terminal, and moreover, the sense amplifier activation and reset time is shortened by limiting the word line activation and sense amplifier activation to the required sub-cell matrix region only. By constructing the command decode section, the row circuit section and the column circuit section in a pipeline structure, consecutive random access operations can be carried out in such a manner that they overlap with respect to the period.
However, in the proposed FCRAM described above, there only exist three commands: READ, WRITE and REFRESH. And there is no separation of Row operation and Column operation by different commands. Consequently, even in cases where data is read out consecutively from the same word line, it is necessary to repeat an operational sequence from the row decode operation through to the reset operation invoked by different read commands. Therefore, even if, for example, the data output rate or data input rate is higher, the access time and access cycle time cannot be shortened. Moreover, in the aforementioned random access operation, the access time and access cycle time become longer than a case where data held in the sense amplifiers is output like a page mode.
Secondly, since there is only one type of read command for the read operation, it is not possible to distinguish from the read command whether data is to be read out consecutively from the same word line, or whether data from a different word line is to be read out. The same applies in the case of a write operation.